`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/08/26 09:50:41
// Design Name: 
// Module Name: pt_sim1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pt_sim1(
    output wire rs,
    output wire wr,
    output wire rd,
    output wire reset,
    output wire csl,
    output wire[7:0] db
    );
    
    reg clk;
    reg rst;
    
    parameter period = 10;
    //parameter half_period = 5;
    
    initial begin
        rst = 1'b1;
        #(period*3/4);
        rst = 1'b0;
    end
    initial begin
        clk = 1'b1;
        forever #(period/2) clk = ~clk;
    end
    initial begin
        #(period*20) $stop;
    end
    
    (* DONT_TOUCH = "TRUE" *) wire[63:0] rom_data;
    (* DONT_TOUCH = "TRUE" *) wire[31:0] rom_addr;
    (* DONT_TOUCH = "TRUE" *) wire rom_ce;
    (* DONT_TOUCH = "TRUE" *) wire[31:0] ram_raddr_1;
    (* DONT_TOUCH = "TRUE" *) wire ram_re_1;
    (* DONT_TOUCH = "TRUE" *) wire[31:0] ram_rdata_1;
    (* DONT_TOUCH = "TRUE" *) wire[31:0] ram_raddr_2;
    (* DONT_TOUCH = "TRUE" *) wire ram_re_2;
    (* DONT_TOUCH = "TRUE" *) wire[31:0] ram_rdata_2;
    (* DONT_TOUCH = "TRUE" *) wire[31:0] ram_waddr;
    (* DONT_TOUCH = "TRUE" *) wire ram_we;
    (* DONT_TOUCH = "TRUE" *) wire[31:0] ram_wdata;
    (* DONT_TOUCH = "TRUE" *) wire[3:0] intf_func;
    (* DONT_TOUCH = "TRUE" *) wire[7:0] intf_data;
    (* DONT_TOUCH = "TRUE" *) wire intf_state;
    
    cpu cpu(
        .rst(rst),
        .clk(clk),
        .rom_data_i(rom_data),
        .rom_addr_o(rom_addr),
        .rom_ce_o(rom_ce),
        .ram_raddr_1_o(ram_raddr_1),
        .ram_re_1_o(ram_re_1),
        .ram_rdata_1_i(ram_rdata_1),
        .ram_raddr_2_o(ram_raddr_2),
        .ram_re_2_o(ram_re_2),
        .ram_rdata_2_i(ram_rdata_2),
        .ram_waddr_o(ram_waddr),
        .ram_we_o(ram_we),
        .ram_wdata_o(ram_wdata),
        .func_o(intf_func),
        .data_o(intf_data),
        .state_i(intf_state)
    );
    
    rom rom(
        .ce(rom_ce),
        .addr(rom_addr),
        .inst(rom_data)
    );
    
    ram ram(
        .rst(rst),
        .clk(clk),
        .raddr_1(ram_raddr_1),
        .re_1(ram_re_1),
        .rdata_1(ram_rdata_1),
        .raddr_2(ram_raddr_2),
        .re_2(ram_re_2),
        .rdata_2(ram_rdata_2),
        .waddr(ram_waddr),
        .we(ram_we),
        .wdata(ram_wdata)
    );
    
    intf_ctrl intf_ctrl(
        .rst(rst),
        .clk(clk),
        .func_i(intf_func),
        .data_i(intf_data),
        .state_o(intf_state),
        .rs(rs),
        .wr(wr),
        .rd(rd),
        .reset(reset),
        .csl(csl),
        .db(db)
    );
    
endmodule
